1. Field of the Invention
The present invention relates to the field of metal-oxide-semiconductor (MOS) electrically programmable and electrically erasable read-only memories (EEPROMs) and to electrically programmable read-only memories (EPROMs) having floating gates.
2. Related Applications
This application relates to copending application Ser. No. 892,446, filed Aug. 4, 1986, and entitled LOW VOLTAGE EEPROM CELL; copending application Ser. No. 07/144567, filed 1-12-88, entitled VOLTAGE MARGINING CIRCUIT FOR FLASH EPROM; copending application Ser. No. 07/144569, filed 1-12-88, entitled LOAD LINE FOR FLASH EPROM; copending application Ser. No. 07/157364, filed 2-17-88, entitled LEAKAGE VERIFICATION FOR FLASH EPROM; copending application Ser. No. 07/157362, filed 2-17-88, entitled PROCESSOR CONTROLLED COMMAND PORT ARCHITECTURE FOR FLASH MEMORY; all assigned to the assignee of the present invention.
3. Prior Art
The most commonly used EPROM cell has an electrically floating gate which is completely surrounded by insulation and generally disposed between a source and drain region formed in a silicon substrate. In earlier versions of these cells, charge is injected through the insulation by avalanche injection such as the device described in U.S. Pat. No. 3,660,819. Later versions of EPROMs relied on channel injection for charging the floating gate as described in U.S. Pat. Nos. 4,142,926; 4,114,255 and 4,412,310. These EPROMs are erased by exposing the array to ultraviolet radiation.
Electrically erasable EPROMs (EEPROMs) are also commercially available. In some cases, charge is placed into and removed from a floating gate by tunnelling the charge through a thin oxide region formed on the substrate (See U.S. Pat. No. 4,203,158). In other instances, charge is removed through an upper electrode (See U.S. Pat. No. 4,099,196).
These EEPROM cells do not lend themselves to being reduced in substrate area as do the EPROM cells. Various techniques have been implemented to reduce the size of the memory array by providing higher-density cells. One such technique is disclosed in U.S. Pat. No. 4,432,075. Further, U.S. Pat. No. 4,266,283 discloses the arrangement of an EEPROM into an array and selection of various functions to be performed on the memory array.
EPROM memories are most often removed from their printed circuit boards for both erasing and programing. A special programming device is used for programming the cells. This device also verifies that the cells have been properly erased and programed. During programing, electrons are transferred to the floating gate making the cells less conductive. The operation of these EPROM devices are well-known.
EEPROMs are different than EPROMs in that EEPROMs are typically programmed and erased while installed in the same circuit (e.g., printed circuit board) used for reading data from the memory. That is, a special programming device is not used. In some cases "on-chip" circuits are used to verify that the programming has been properly performed. U.S. Pat. No. 4,460,982 discloses an intelligent EEPROM which provides means for both programming and erasing.
More recently, a new category of electrically erasable EPROMs/EEPROMs has emerged and these devices are sometimes referred to as "Flash" EPROMs or EEPROMs. In these flash memories, the entire array is simultaneously erased, electrically. The cells themselves use only a single device per cell and such cell are described in the fore-mentioned copending application Ser. No. 892,446. Another relevant art is an article entitled "A 256-kbit Flash E.sup.2 PROM Using Triple-Polysilicon Technology", Masuoka et al., IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 4, August, 1987. The present invention is directed towards the use of these cells.
Electrically erasing flash memory devices gives rise to another problem, specifically over-erasing. Too much charge can be removed, making the device "depletion-like". Cells may require testing after being erased to verify that the floating gate is erased, but not too positively charged.
Another problem is encountered when in circuit erasing is used on the flash memories. Additional signal/command lines are needed to provide for the erasing and programming of the flash memory. Typically additional lines, which require additional pins on a memory chip, are not a problem when designing new circuits, boards, systems, etc. However, for the flash memories to be used in place of existing EPROMs/EEPROMs, pin-to-pin compatibility is a must requirement. Because additional control lines for erasing and programming are needed, a direct pin-to-pin compatibility cannot be achieved unless certain architectural changes are made within the flash memory device which permits the erasing and reprogramming.